IJSRD - International Journal for Scientific Research amp; Development| Vol. 3, Issue 05, 2015 | ISSN (online): 2321-0613
VLSI Implementation of Low Power Area Efficient FIR Digital Filter
Structures
Shaila Khan1 Uma Sharma2
1M.Tech Student 2Assistant Professor
1,2Department of Electronics and Communication Engineering
1Ajay Kumar Garg Engineering College, Ghaziabad, India
Abstract— Filter occupies a major role in digital signal processing. The design of parallel FIR filter structures using Common sub expression elimination technique requires minimum number of multipliers and low power adders. As normally multiplier consume more area and power in comparison of adder. Moreover, along with the increase in length of parallel FIR filter number of adders does not increases. By using common sub expression elimination algorithms, the adopted parallel FIR structures use the basic nature of symmetric coefficients which reduces half the number of multipliers in Sub-Filter section at the amount of additional adders in preprocessing and post processing blocks. In term of silicon area, the weight of multiplier is more than adder so exchanging multipliers with adders is advantageous. Finally the proposed parallel FIR filter structures are superior from existing one in terms of consumption of area and power.
Key words:
I. INTRODUCTION
The finite-impulse response (FIR) filter has been and continues to be one of the fundamental processing elements in any digital signal processing (DSP) system.FIR filters are used in DSP applications that range from video and image processing to wireless communications. In some applications, such as video processing, the FIR filter circuit must be able to operate at high frequencies, while in other applications, such as cellular telephony, the FIR filter circuit must be a low-power circuit, capable of operating at moderate frequencies. Parallel, or block, processing can be applied to digital FIR filters to either increase the effective throughput or reduce the power consumption of the original filter. Traditionally, the application of parallel processing to a FIR filter involves the replication of the hardware units that exist in the original filter. If the area required by the original circuit is A, then the L-parallel circuit requires an area of L x A. With the continuing trend to reduce chip size and integrate multi-chip solutions into a single chip solution, it is important to limit the silicon area required to implement a parallel FIR digital filter in a VLSI implementation. In many design situations, the hardware overhead that is incurred by parallel processing cannot be tolerated due to limitations in design area. Therefore, it is advantageous to realize parallel FIR filtering structures that consume less area than traditional parallel FIR filtering structures. There have been a few papers proposing ways to reduce the complexity of the parallel FIR filter in the past [1]–[9]. In [1]–[4], polyphase decomposition is mainly manipulated, where the small-sized parallel FIR filter structures are derived first and then the larger block-sized ones can be constructed by cascading or iterating small-sized parallel FIR filtering blocks. Fast FIR algorithms (FFAs) introduced in [1]–[3] shows that it can implement a L-parallel filter
using approximately (2L-1) sub filter blocks, each of which is of length N/L. FFA structures successfully break the constraint that the hardware implementation cost of a parallel FIR filter has a linear increase along with the block size L. It reduces the required number of multipliers to (2N-N/L) from LXN. In [5]–[9], the fast linear convolution is utilized to develop the small-sized filtering structures and then a long convolution is decomposed into several short convolutions, i.e., larger block-sized filtering structures can be constructed through iterations of the small-sized filtering structures. On the other hand, parallel and pipelining processing are two techniques used in DSP applications, which can both be exploited to reduce the power consumption. Pipelining shortens the critical path by interleaving pipelining latches along the data path, at the price of increasing the number of latches and the system latency, whereas parallel processing increase the sampling rate by replicating hardware so that multiple inputs can be processed in parallel and multiple outputs are generated at the same time, at the expense of increased area. Both techniques can reduce the power consumption by lowering the supply voltage, where the sampling speed does not increase. In this paper, parallel processing in the digital FIR filter will be discussed.
II. WINDOW METHOD FOR FIR FILTER DESIGN
The window method is the fast, easy and robust for FIR Filter digital but generally ordinary. By the convolution theorem of Fourier transforms it can easily be understood, making it informative to study after the windows for spectrum analysis and Fourier theorems.
[-N, N]
We would expect to be able to change the length of Filter to the interval, for some sufficiently large N, and obtain a good FIR filter which approximates the ideal filter. This would be an example of using the window method with the rectangular window. We can manage various trade-off by choosing the window carefully, so as to maximize the filter-design quality in a given application. The functions of Window are always time limited. Always FIR filter is design by window method rather than IIR filter. By using dual of the convolution theorem, point wise multiplication in the time domain corresponds to convolution in the frequency domain.
III. PARALLEL PROCESSING FOR LOW POWER
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VLSI Implementation of Low Power Area Efficient FIR Digital Filter
Structures
Shaila Khan1 Uma Sharma2
1M.Tech Student 2Assistant Professor
1,2Department of Electronics and Communication Engineering
1Ajay Kumar Garg Engineering College, Ghaziabad, India
VLSI 实现 低功率区效率的FIR滤波器结构
Shaila Khan1 Uma Sharma2
M.Tech 学生助理教授
电子与通信工程系
Ajay加戈工程学院,阿巴德,印度
Abstract— Filter occupies a major role in digital signal processing. The design of parallel FIR filter structures using Common sub expression elimination technique requires minimum number of multipliers and low power adders. As normally multiplier consume more area and power in comparison of adder. Moreover, along with the increase in length of parallel FIR filter number of adders does not increases. By using common sub expression elimination algorithms, the adopted parallel FIR structures use the basic nature of symmetric coefficients which reduces half the number of multipliers in Sub-Filter section at the amount of additional adders in preprocessing and post processing blocks. In term of silicon area, the weight of multiplier is more than adder so exchanging multipliers with adders is advantageous. Finally the proposed parallel FIR filter structures are superior from existing one in terms of consumption of area and power.
Key words: FIR Digital Filter Multipliers Adders
摘要——滤波器在数字信号处理中占有重要的地位。通用子表达式消除技术的并行滤波器结构的设计要求最少的乘法器和低功率加法器。一般来说，乘数器比加法器要消耗更多的面积和能量。此外，随着FIR滤波器的长度的增加，加法器的数量也不会增加。并行FIR结构使用对称系数的基本性质可以减少一半的乘数器在子滤波器部分中的额外的加法器的数量上在预处理和后期处理块中。在硅领域，乘法器的重量大于加法器，因此把乘数器换成加法器是有利的。最后，提出的并行FIR滤波器结构在面积和功率消耗方面优于现有的。
关键词：FIR数字滤波器 乘法器 加法器
I. INTRODUCTION
The finite-impulse response (FIR) filter has been and continues to be one of the fundamental processing elements in any digital signal processing (DSP) system.FIR filters are used in DSP applications that range from video and image processing to wireless communications. In some applications, such as video processing, the FIR filter circuit must be able to operate at high frequencies, while in other applications, such as cellular telephony, the FIR filter circuit must be a low-power circuit, capable of operating at moderate frequencies. Parallel, or block, processing can be applied to digital FIR filters to either increase the effective throughput or reduce the power consumption of the original filter. Traditionally, the application of parallel processing to a FIR filter involves the replication of the hardware units that exist in the original filter. If the area required by the original circuit is A, then the L-parallel circuit requires an area of L x A. With the continuing trend to reduce chip size and integrate multi-chip solutions into a single chip solution, it is important to limit the silicon area required to implement a parallel FIR digital filter in a VLSI implementation. In many design situations, the hardware overhead that is incurred by parallel processing cannot be tolerated due to limitations in design area. Therefore, it is advantageous to realize parallel FIR filtering structures that consume less area than traditional parallel FIR filtering structures. There have been a few papers proposing ways to reduce the complexity of the parallel FIR filter in the past [1]–[9]. In [1]–[4], polyphase decomposition is mainly manipulated, where the small-sized parallel FIR filter structures are derived first and then the larger block-sized ones can be constructed by cascading or iterating small-sized parallel FIR filtering blocks. Fast FIR algorithms (FFAs) introduced in [1]–[3] shows that it can implement a L-parallel filter using approximately (2L-1) sub filter blocks, each of which is of length N/L. FFA structures successfully break the constraint that the hardware implementation cost of a parallel FIR filter has a linear increase along with the block size L. It reduces the required number of multipliers to (2N-N/L) from LXN. In [5]–[9], the fast linear convolution is utilized to develop the small-sized filtering structures and then a long convolution is decomposed into several short convolutions, i.e., larger block-sized filtering structures can be constructed through iterations of the small-sized filtering structures. On the other hand, parallel and pipelining processing are two techniques used in DSP applications, which can both be exploited to reduce the power consumption. Pipelining shortens the critical path by interleaving pipelining latches along the data path, at the price of increasing the number of latches and the system latency, whereas parallel processing increase the sampling rate by replicating hardware so that multiple inputs can be processed in parallel and multiple outputs are generated at the same time, at the expense of increased area. Both techniques can reduce the power consumption by lowering the supply voltage, where the sampling speed does not increase. In this paper, parallel processing in the digital FIR filter will be discussed.
1.概述
在任何数字信号处理(DSP)系统中有限脉冲响应(FIR)滤波器已经实现并继续适用的基本的处理元素之一。FIR滤波器用于DSP应用，从视频和图像处理到无线通信。在某些应用程序中,如视频处理,FIR滤波电路必须能够运行在高频率,而在其他应用程序,如移动电话、FIR滤波电路必须是低功耗电路,能够在中等频率下工作。并行或块状处理可应用于数字FIR滤波器，既可提高有效生产量，又可降低原始滤波器的功耗。传统上，将并行处理应用到FIR滤波器中涉及到原始滤波器中存在的硬件单元的复制。如果原始电路所要求的面积是A，那么L-平行电路需要一个L x A的面积。随着降低芯片尺寸，并将多芯片解决方案集成到单个芯片解决方案中的持续的趋势，限制在超大规模集成电路实现中实现平行的冷杉数字滤波器是很重要的。在许多设计场景中，由于设计领域的限制，并行处理所产生的硬件开销是不可容忍的。
因此，与实现传统的平行FIR滤波器结构相比，具有较少面积的平行FIR滤波器结构是有利的。有一些章节提出减少并行FIR滤波器的复杂性的方法在[1]-[9]。在[1]-[4],多相分解主要是被操纵的,小型并行FIR滤波器结构是最早衍生的,然后可以构造更大的块尺寸FIR滤波通过级联或小型并行迭代FIR过滤块。快速FIR算法(FFAs)在[1]-[3]中引入，这表明,它可以实现L-平行滤波器，它使用约(2 L - 1)子滤波器模块,每个长度N / L。FFA结构成功地打破了一个约束，即并行FIR滤波器的硬件实现成本与块大小L有线性增长。它从LXN减少所需乘法器的数量到 (2N-N/L)。在[5]-[9],快速线性卷积是利用开发小型滤波器结构,然后长卷积分解成几个
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